GR-CPCI-LEON4-N2X

Quad-Core LEON4 Next Generation Microprocessor Evaluation Board

The GR-CPCI-LEON4-N2X evaluation board has been designed for evaluation of the Aeroflex Gaisler LEON4 Next Generation Microprocessor (NGMP) functional prototype device. The NGMP functional prototype is a system-on-chip with four 32-bit LEON4 SPARC V8 processor cores connected to a shared 256 KiB Level-2 cache and several high-speed interfaces, including an 8-port SpaceWire router and dual gigabit Ethernet interfaces. The architecture provides improved support for debugging and software partitioning together with extended support for both symmetric and asymmetric multiprocessing.

The board is a custom designed PCB in a 6U Compact PCI (CPCI) format, making the board suitable for stand-alone bench top development, or if required, to be mounted in a 6U CPCI Rack. The principle interfaces and functions are accessible on the front and back edges of the board, and secondary interfaces via headers on the board.

For further information about this board, or for information on the LEON4 processor, please see Aeroflex Gaisler web-site for this product:GR-CPCI-LEON4-N2X

Board Features:

• Quad-Core 32-bit LEON4 SPARC V8 processor
• 6U Compact PCI format
• On board memory
• DDR2 SDRAM SODIMM sockets, providing 96-bit wide interface with up to 2 GiB of data memory
• PPC100 SDRAM, 96-bit wide interface providing 128 MiB of data memory
• NOR Flash PROM, 8 MiB, both 8- and 16-bit wide operation
• Debug communication links: SpaceWire, USB 2.0, Ethernet, JTAG
• Interfaces at front edge of board:
• Dual 10/100/1000 Mbit Ethernet interface
• Dual-redundant MIL-STD-1553B interface
• 8-port SpaceWire interface
• SpaceWire Debug Communication Link interface
• 16 bit General Purpose I/O (ribbon cable style connector)
• USB-to-Serial interface providing access to UARTs and JTAG debug interface
• Interfaces at back edge of board:
• Compact PCI interface (32 bit, 33/66MHz), configurable for Host or Peripheral slot
• Input power connectors for stand-alone use
• Interfaces on board:
• DIP switches for GPIO and bootstrap signal configuration
• LED indicators
• SPI interface
• Two Serial UART interface (RS232)
• JTAG debug interface

User Manual:

GR-CPCI-LEON4-N2X_user_manual_AG.pdf

Assembly Drawing:

GR-CPCI-LEON4-N2X_assy_dwg.pdf

Technical Note about Mezzanine Connectors:

GR-MEZZ_Technical_Note.pdf

For sales or pricing information about this board, or for information on the LEON4 processor, please contact: sales@gaisler.com

BACK TO BOARDS